1. Field of the Invention
This invention relates to a non-volatile semiconductor memory such as a flash EEPROM (Electrically Erasable Programmable Read Only Memory) which has an auto-function for automatically writing or erasing data.
2. Description of the Related Art
Recently, flash EEPROMs (hereinafter referred to as "flash memories") have been widely developed and used as memory cards or in place of magnetic disk devices. Flash memories of this type are each controlled by a processor installed in an apparatus together with the memory. Many of the flash memories have auto-functions (program and erase sequence controller) for reducing the amount of load applied to processors. One of the flash memories with auto-functions is disclosed, for example, in 1991 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 260 and 261 Nakayama et al. "A 60 ns 16 Mb Flash EEPROM with Program and Erase Sequence Controller".
The auto-function enables the flash memory to automatically perform a sequence of data-write/erase operations therein. Specifically, upon receiving from the processor a command for causing the flash memory to perform a predetermined write or erase operation, the flash memory operates in accordance with the command and transmits a status signal indicative of whether or not it has been normally operated. Thus, what the processor does after transmitting the command to the flash memory is only to wait for the status signal from the memory and estimate the value of the status signal. This means the processor performs only simple processing. Further, the flash memory, which operates independent of the operation of the processor, can perform delicate control.
FIG. 1 is a flowchart showing a sequence of operations performed by the auto-function of the flash memory. The flash memory first analyzes a command transmitted from the processor (step ST1). If the command indicates that data should be written in a memory cell with a predetermined address, the flash memory latches the address and data, and performs a set-up operation for setting a programming voltage (step ST2). Thereafter, a busy signal indicating that the flash memory is now operating is outputted, and the counter is cleared (N=0) (step ST3). Subsequently, a write pulse indicative of the programming voltage is transmitted to the designated memory cell, thereby executing a predetermined program for e.g. 10 .mu.s. Then, the value of the counter is incremented (N=N+1) (step ST4). After the program is terminated, the data written in the memory cell is read and verified (step ST5). If it is determined, as a result of verify, that the data has been correctly (normally) written, a status signal indicative of the termination of normal writing is set (step ST6), and the busy signal is reset (step ST7). On the other hand, if it is determined that the data has been incorrectly written, the same data is rewritten into the same memory cell, and verify is performed again. The rewrite and re-verify, which will hereinafter be called "retrial", is repeated 25 times at maximum (N=25) (step ST8). If the verify operation does not show a good result during 25 repetitions of retrial, the status signal indicative of the termination of normal write is not set, and only the busy signal is reset (step ST7). The processor determines that the write operation has been normally terminated if the status signal transmitted from the flash memory is set, and determines that the write operation has failed if the status signal is not set.
Conventional semiconductor memories as described above are subjected to various examinations after being manufactured, in order to eliminate defects therein. In the case of the memories other than the flash memories, each of which has a control circuit simple in structure as compared with the flash memories, most transistors employed in each memory can be activated by performing various write/read operations in all memory cells, thereby detecting defects in the memory at a detection rate of almost 100%. On the other hand, the flash memory with the auto-function has a complicated control circuit for performing various operations therein. Moreover, the auto-function executes write or erase in a predetermined sequence, and whether or not the verify result obtained after programming is normal depends upon the characteristics (write and erase characteristics) of each memory cell. Therefore, it is possible depending upon the memory cell characteristics that only part of the control circuit operates, and it is difficult to activate the entire control circuit. Accordingly, the detection rate of a defect is inevitably low.
For example, as is shown in FIG. 2, there can be a defect DEF1, as indicated by an equivalent resistor, at the output terminal of a flip-flop circuit 25a located in the last stage of a counter 25 for counting the number of repetitions of retrial. Further, there can be a defect DEF2, as indicated by an equivalent resistor, in the input stage of a control circuit 24a for setting a status signal when the first-time write operation has been terminated. In these cases, it is difficult to detect the defects DEF1 and DEF2, depending upon the memory cell characteristics.
More specifically, if there is no defect in the circuit, the flip-flop circuit 25a located in the last stage of the counter 25 generates a low-level signal when retrial has been repeated 16 times. On the other hand, in the case where there is the defect DEF1 at the output terminal of the flip-flop circuit 25a, the value of the counter 25 becomes 25 (N=25) when retrial has been repeated, for example, 9 times, followed by the termination of the program. Accordingly, if all memory cells of the memory have good write characteristics in which data can be correctly written in each of the memory cells in one routine of the program, the flip-flop circuit 25a does not operate and hence the defect DEF1 cannot be detected. Only where the memory has a memory cell which needs more than 9 repetitions of retrial, the defect DEF1 can be detected.
On the other hand, an AND circuit 24b connected to the input terminal of the control circuit 24a outputs a high-level signal when a high-level signal indicative of normal writing has been output from the verify circuit 21, and when a signal indicative of first-time writing has been output from the counter 25. Accordingly, if the memory cells can perform normal write in one write routine, the defect DEF2 can be detected. If, however, the memory cells have bad write characteristics in which they need 5 or 6 repetitions of retrial, the control circuit 24a does not operate and hence the defect DEF2 cannot be detected.
As explained above, in the flash memory with the conventional auto-function, the circuit for executing the auto-function cannot be controlled from the outside, and the determination whether or not the verify result after programming is normal depends upon the write or erase characteristics of memory cells, which makes it difficult to detect defects in the memory in a reliable manner. Moreover, if the flash memory has the defect DEF1 and all memory cells can be programmed by a small number of repetitions of retrial, it can be said that the memory has a satisfactory function in an initial stage. In this case, however, the write and/or erase characteristics of each memory cell will be degraded after a large number of repetitions of retrial, with the result that there is a possibility of occurrence of malfunction due to the defect DEF1. To avoid this, it is requested that a memory with no defects be produced.